Fin field-effect transistors (FinFET) devices have been developed to replace conventional planar bulk MOSFETs in advanced CMOS technology due to their improved short-channel effect immunity and Ion/Ioff ratio. However, a problem with bulk short channel FinFET devices, is that a leakage path from source to drain exists through a portion of the fin not covered by the gate, but lies below the channel. The leakage of current from source to drain through the lower (un-gated) part of the fin that is not covered by the gate, commonly known as punch-through leakage, causes an increase of static power consumption which is undesirable in modern submicron devices.
In one solution, punch-through leakage in submicron semiconductor devices is sought to be controlled by implanting a punch-through-stopper (PTS) dopant in a portion of the fin directly below the channel. However, the impurities doped by the punch-through-stopper (PTS) implantation may diffuse into the channel region, increasing the variability due to random dopant fluctuation (RDF) and lowering the carrier mobility of the channel region.
There is a need for improved methods for forming FinFETs with reduce punch-through leakage.